// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  smmu_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  gaojianbo
// Version       :  1
// Date          :  2016/6/6
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  gaojianbo 2018/04/10 11:38:00 Create file
// ******************************************************************************

#ifndef __SMMU_REG_OFFSET_FIELD_H__
#define __SMMU_REG_OFFSET_FIELD_H__

#define SMMU_RAS_LEN            1
#define SMMU_RAS_OFFSET         29
#define SMMU_ST_LEVEL_LEN       2
#define SMMU_ST_LEVEL_OFFSET    27
#define SMMU_TERM_MODEL_LEN     1
#define SMMU_TERM_MODEL_OFFSET  26
#define SMMU_STALL_MODEL_LEN    2
#define SMMU_STALL_MODEL_OFFSET 24
#define SMMU_TTENDIAN_LEN       2
#define SMMU_TTENDIAN_OFFSET    21
#define SMMU_VATOS_LEN          1
#define SMMU_VATOS_OFFSET       20
#define SMMU_CD2L_LEN           1
#define SMMU_CD2L_OFFSET        19
#define SMMU_VMID16_LEN         1
#define SMMU_VMID16_OFFSET      18
#define SMMU_VMW_LEN            1
#define SMMU_VMW_OFFSET         17
#define SMMU_PRI_LEN            1
#define SMMU_PRI_OFFSET         16
#define SMMU_ATOS_LEN           1
#define SMMU_ATOS_OFFSET        15
#define SMMU_SEV_LEN            1
#define SMMU_SEV_OFFSET         14
#define SMMU_MSI_LEN            1
#define SMMU_MSI_OFFSET         13
#define SMMU_ASID16_LEN         1
#define SMMU_ASID16_OFFSET      12
#define SMMU_NS1ATS_LEN         1
#define SMMU_NS1ATS_OFFSET      11
#define SMMU_ATS_LEN            1
#define SMMU_ATS_OFFSET         10
#define SMMU_HYP_LEN            1
#define SMMU_HYP_OFFSET         9
#define SMMU_DORMHINT_LEN       1
#define SMMU_DORMHINT_OFFSET    8
#define SMMU_HTTU_LEN           2
#define SMMU_HTTU_OFFSET        6
#define SMMU_BTM_LEN            1
#define SMMU_BTM_OFFSET         5
#define SMMU_COHACC_LEN         1
#define SMMU_COHACC_OFFSET      4
#define SMMU_TTF_LEN            2
#define SMMU_TTF_OFFSET         2
#define SMMU_S1P_LEN            1
#define SMMU_S1P_OFFSET         1
#define SMMU_S2P_LEN            1
#define SMMU_S2P_OFFSET         0

#define SMMU_TABLES_PRESET_LEN     1
#define SMMU_TABLES_PRESET_OFFSET  30
#define SMMU_QUEUES_PRESET_LEN     1
#define SMMU_QUEUES_PRESET_OFFSET  29
#define SMMU_REL_LEN               1
#define SMMU_REL_OFFSET            28
#define SMMU_ATTR_TYPES_OVR_LEN    1
#define SMMU_ATTR_TYPES_OVR_OFFSET 27
#define SMMU_ATTR_PERMS_OVR_LEN    1
#define SMMU_ATTR_PERMS_OVR_OFFSET 26
#define SMMU_CMDQS_LEN             5
#define SMMU_CMDQS_OFFSET          21
#define SMMU_EVENTQS_LEN           5
#define SMMU_EVENTQS_OFFSET        16
#define SMMU_PRIQS_LEN             5
#define SMMU_PRIQS_OFFSET          11
#define SMMU_SSIDSIZE_LEN          5
#define SMMU_SSIDSIZE_OFFSET       6
#define SMMU_SIDSIZE_LEN           6
#define SMMU_SIDSIZE_OFFSET        0

#define SMMU_BA_VATOS_LEN    10
#define SMMU_BA_VATOS_OFFSET 0

#define SMMU_HAD_LEN    1
#define SMMU_HAD_OFFSET 2



#define SMMU_STALL_MAX_LEN    16
#define SMMU_STALL_MAX_OFFSET 16
#define SMMU_GRAN64K_LEN      1
#define SMMU_GRAN64K_OFFSET   6
#define SMMU_GRAN16K_LEN      1
#define SMMU_GRAN16K_OFFSET   5
#define SMMU_GRAN4K_LEN       1
#define SMMU_GRAN4K_OFFSET    4
#define SMMU_OAS_LEN          3
#define SMMU_OAS_OFFSET       0

#define SMMU_PRODUCTID_LEN      12
#define SMMU_PRODUCTID_OFFSET   20
#define SMMU_VARIANT_LEN        4
#define SMMU_VARIANT_OFFSET     16
#define SMMU_REVISION_LEN       4
#define SMMU_REVISION_OFFSET    12
#define SMMU_IMPLEMENTER_LEN    12
#define SMMU_IMPLEMENTER_OFFSET 0

#define SMMU_ARCHMAJORREV_LEN    4
#define SMMU_ARCHMAJORREV_OFFSET 4
#define SMMU_ARCHMINORREV_LEN    4
#define SMMU_ARCHMINORREV_OFFSET 0

#define SMMU_VMW_LEN         3
#define SMMU_VMW_OFFSET      6
#define SMMU_ATSCHK_LEN      1
#define SMMU_ATSCHK_OFFSET   4
#define SMMU_CMDQEN_LEN      1
#define SMMU_CMDQEN_OFFSET   3
#define SMMU_EVENTQEN_LEN    1
#define SMMU_EVENTQEN_OFFSET 2
#define SMMU_PRIQEN_LEN      1
#define SMMU_PRIQEN_OFFSET   1
#define SMMU_SMMUEN_LEN      1
#define SMMU_SMMUEN_OFFSET   0

#define SMMU_VMW_LEN         3
#define SMMU_VMW_OFFSET      6
#define SMMU_ATSCHK_LEN      1
#define SMMU_ATSCHK_OFFSET   4
#define SMMU_CMDQEN_LEN      1
#define SMMU_CMDQEN_OFFSET   3
#define SMMU_EVENTQEN_LEN    1
#define SMMU_EVENTQEN_OFFSET 2
#define SMMU_PRIQEN_LEN      1
#define SMMU_PRIQEN_OFFSET   1
#define SMMU_SMMUEN_LEN      1
#define SMMU_SMMUEN_OFFSET   0

#define SMMU_TABLE_SH_LEN    2
#define SMMU_TABLE_SH_OFFSET 10
#define SMMU_TABLE_OC_LEN    2
#define SMMU_TABLE_OC_OFFSET 8
#define SMMU_TABLE_IC_LEN    2
#define SMMU_TABLE_IC_OFFSET 6
#define SMMU_QUEUE_SH_LEN    2
#define SMMU_QUEUE_SH_OFFSET 4
#define SMMU_QUEUE_OC_LEN    2
#define SMMU_QUEUE_OC_OFFSET 2
#define SMMU_QUEUE_IC_LEN    2
#define SMMU_QUEUE_IC_OFFSET 0

#define SMMU_PTM_LEN          1
#define SMMU_PTM_OFFSET       2
#define SMMU_RECINVSID_LEN    1
#define SMMU_RECINVSID_OFFSET 1
#define SMMU_E2H_LEN          1
#define SMMU_E2H_OFFSET       0

#define SMMU_DORMANT_LEN    1
#define SMMU_DORMANT_OFFSET 0

#define SMMU_UPDATING_LEN    1
#define SMMU_UPDATING_OFFSET 31
#define SMMU_ABORT_LEN       1
#define SMMU_ABORT_OFFSET    20
#define SMMU_INSTCFG_LEN     2
#define SMMU_INSTCFG_OFFSET  18
#define SMMU_PRIVCFG_LEN     2
#define SMMU_PRIVCFG_OFFSET  16
#define SMMU_SHCFG_LEN       2
#define SMMU_SHCFG_OFFSET    12
#define SMMU_ALLOCCFG_LEN    4
#define SMMU_ALLOCCFG_OFFSET 8
#define SMMU_MTCFG_LEN       1
#define SMMU_MTCFG_OFFSET    4
#define SMMU_MEMATTR_LEN     4
#define SMMU_MEMATTR_OFFSET  0

#define SMMU_UPDATING_LEN    1
#define SMMU_UPDATING_OFFSET 31
#define SMMU_ABORT_LEN       1
#define SMMU_ABORT_OFFSET    20
#define SMMU_INSTCFG_LEN     2
#define SMMU_INSTCFG_OFFSET  18
#define SMMU_PRIVCFG_LEN     2
#define SMMU_PRIVCFG_OFFSET  16
#define SMMU_SHCFG_LEN       2
#define SMMU_SHCFG_OFFSET    12
#define SMMU_ALLOCCFG_LEN    4
#define SMMU_ALLOCCFG_OFFSET 8
#define SMMU_MTCFG_LEN       1
#define SMMU_MTCFG_OFFSET    4
#define SMMU_MEMATTR_LEN     4
#define SMMU_MEMATTR_OFFSET  0

#define SMMU_EVENTQ_IRQEN_LEN    1
#define SMMU_EVENTQ_IRQEN_OFFSET 2
#define SMMU_PRIQ_IRQEN_LEN      1
#define SMMU_PRIQ_IRQEN_OFFSET   1
#define SMMU_GERROR_IRQEN_LEN    1
#define SMMU_GERROR_IRQEN_OFFSET 0

#define SMMU_EVENTQ_IRQEN_LEN    1
#define SMMU_EVENTQ_IRQEN_OFFSET 2
#define SMMU_PRIQ_IRQEN_LEN      1
#define SMMU_PRIQ_IRQEN_OFFSET   1
#define SMMU_GERROR_IRQEN_LEN    1
#define SMMU_GERROR_IRQEN_OFFSET 0

#define SMMU_MSI_GERROR_ABT_ERR_LEN    1
#define SMMU_MSI_GERROR_ABT_ERR_OFFSET 7
#define SMMU_MSI_PRIQ_ABT_ERR_LEN      1
#define SMMU_MSI_PRIQ_ABT_ERR_OFFSET   6
#define SMMU_MSI_EVENTQ_ABT_ERR_LEN    1
#define SMMU_MSI_EVENTQ_ABT_ERR_OFFSET 5
#define SMMU_MSI_CMDQ_ABT_ERR_LEN      1
#define SMMU_MSI_CMDQ_ABT_ERR_OFFSET   4
#define SMMU_PRIQ_ABT_ERR_LEN          1
#define SMMU_PRIQ_ABT_ERR_OFFSET       3
#define SMMU_EVENTQ_ABT_ERR_LEN        1
#define SMMU_EVENTQ_ABT_ERR_OFFSET     2
#define SMMU_CMDQ_ERR_LEN              1
#define SMMU_CMDQ_ERR_OFFSET           0

#define SMMU_MSI_GERROR_ABT_ERR_LEN    1
#define SMMU_MSI_GERROR_ABT_ERR_OFFSET 7
#define SMMU_MSI_PRIQ_ABT_ERR_LEN      1
#define SMMU_MSI_PRIQ_ABT_ERR_OFFSET   6
#define SMMU_MSI_EVENTQ_ABT_ERR_LEN    1
#define SMMU_MSI_EVENTQ_ABT_ERR_OFFSET 5
#define SMMU_MSI_CMDQ_ABT_ERR_LEN      1
#define SMMU_MSI_CMDQ_ABT_ERR_OFFSET   4
#define SMMU_PRIQ_ABT_ERR_LEN          1
#define SMMU_PRIQ_ABT_ERR_OFFSET       3
#define SMMU_EVENTQ_ABT_ERR_LEN        1
#define SMMU_EVENTQ_ABT_ERR_OFFSET     2
#define SMMU_CMDQ_ERR_LEN              1
#define SMMU_CMDQ_ERR_OFFSET           0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_RESERVERD_LEN    16
#define SMMU_RESERVERD_OFFSET 16
#define SMMU_ADDR_LEN         16
#define SMMU_ADDR_OFFSET      0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_ADDR_LEN    26
#define SMMU_ADDR_OFFSET 6

#define SMMU_RA_LEN      1
#define SMMU_RA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_FMT_LEN         2
#define SMMU_FMT_OFFSET      16
#define SMMU_SPLIT_LEN       5
#define SMMU_SPLIT_OFFSET    6
#define SMMU_LOG2SIZE_LEN    6
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_ADDR_LEN        27
#define SMMU_ADDR_OFFSET     5
#define SMMU_LOG2SIZE_LEN    5
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_RA_LEN      1
#define SMMU_RA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_WR_WRAP_LEN    1
#define SMMU_WR_WRAP_OFFSET 19
#define SMMU_WR_LEN         19
#define SMMU_WR_OFFSET      0

#define SMMU_ERR_LEN        7
#define SMMU_ERR_OFFSET     24
#define SMMU_RD_WRAP_LEN    1
#define SMMU_RD_WRAP_OFFSET 19
#define SMMU_RD_LEN         19
#define SMMU_RD_OFFSET      0

#define SMMU_ADDR_LEN        27
#define SMMU_ADDR_OFFSET     5
#define SMMU_LOG2SIZE_LEN    5
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_WA_LEN      1
#define SMMU_WA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_OVFLG_LEN      1
#define SMMU_OVFLG_OFFSET   31
#define SMMU_WR_WRAP_LEN    1
#define SMMU_WR_WRAP_OFFSET 19
#define SMMU_WR_LEN         19
#define SMMU_WR_OFFSET      0

#define SMMU_OVACKFLG_LEN    1
#define SMMU_OVACKFLG_OFFSET 31
#define SMMU_RD_WRAP_LEN     1
#define SMMU_RD_WRAP_OFFSET  19
#define SMMU_RD_LEN          19
#define SMMU_RD_OFFSET       0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_ADDR_LEN        27
#define SMMU_ADDR_OFFSET     5
#define SMMU_LOG2SIZE_LEN    5
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_WA_LEN      1
#define SMMU_WA_OFFSET   30
#define SMMU_ADDR_LEN    20
#define SMMU_ADDR_OFFSET 0

#define SMMU_OVFLG_LEN      1
#define SMMU_OVFLG_OFFSET   31
#define SMMU_WR_WRAP_LEN    1
#define SMMU_WR_WRAP_OFFSET 19
#define SMMU_WR_LEN         19
#define SMMU_WR_OFFSET      0

#define SMMU_OVACKFLG_LEN    1
#define SMMU_OVACKFLG_OFFSET 31
#define SMMU_RD_WRAP_LEN     1
#define SMMU_RD_WRAP_OFFSET  19
#define SMMU_RD_LEN          19
#define SMMU_RD_OFFSET       0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_LO_LEN         1
#define SMMU_LO_OFFSET      31
#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_STALL_MODEL_LEN    2
#define SMMU_STALL_MODEL_OFFSET 24
#define SMMU_MSI_LEN            1
#define SMMU_MSI_OFFSET         13

#define SMMU_SECURE_IMPL_LEN    1
#define SMMU_SECURE_IMPL_OFFSET 31
#define SMMU_S_SIDSIZE_LEN      6
#define SMMU_S_SIDSIZE_OFFSET   0



#define SMMU_NSSTALLD_LEN    1
#define SMMU_NSSTALLD_OFFSET 9
#define SMMU_SIF_LEN         1
#define SMMU_SIF_OFFSET      5
#define SMMU_CMDQEN_LEN      1
#define SMMU_CMDQEN_OFFSET   3
#define SMMU_EVENTQEN_LEN    1
#define SMMU_EVENTQEN_OFFSET 2
#define SMMU_SMMUEN_LEN      1
#define SMMU_SMMUEN_OFFSET   0

#define SMMU_NSSTALLD_LEN    1
#define SMMU_NSSTALLD_OFFSET 9
#define SMMU_SIF_LEN         1
#define SMMU_SIF_OFFSET      5
#define SMMU_CMDQEN_LEN      1
#define SMMU_CMDQEN_OFFSET   3
#define SMMU_EVENTQEN_LEN    1
#define SMMU_EVENTQEN_OFFSET 2
#define SMMU_SMMUEN_LEN      1
#define SMMU_SMMUEN_OFFSET   0

#define SMMU_TABLE_SH_LEN    2
#define SMMU_TABLE_SH_OFFSET 10
#define SMMU_TABLE_OC_LEN    2
#define SMMU_TABLE_OC_OFFSET 8
#define SMMU_TABLE_IC_LEN    2
#define SMMU_TABLE_IC_OFFSET 6
#define SMMU_QUEUE_SH_LEN    2
#define SMMU_QUEUE_SH_OFFSET 4
#define SMMU_QUEUE_OC_LEN    2
#define SMMU_QUEUE_OC_OFFSET 2
#define SMMU_QUEUE_IC_LEN    2
#define SMMU_QUEUE_IC_OFFSET 0

#define SMMU_PTM_LEN          1
#define SMMU_PTM_OFFSET       2
#define SMMU_RECINVSID_LEN    1
#define SMMU_RECINVSID_OFFSET 1

#define SMMU_INV_ALL_LEN    1
#define SMMU_INV_ALL_OFFSET 0

#define SMMU_UPDATING_LEN    1
#define SMMU_UPDATING_OFFSET 31
#define SMMU_ABORT_LEN       1
#define SMMU_ABORT_OFFSET    20
#define SMMU_INSTCFG_LEN     2
#define SMMU_INSTCFG_OFFSET  18
#define SMMU_PRIVCFG_LEN     2
#define SMMU_PRIVCFG_OFFSET  16
#define SMMU_NSCFG_LEN       2
#define SMMU_NSCFG_OFFSET    14
#define SMMU_SHCFG_LEN       2
#define SMMU_SHCFG_OFFSET    12
#define SMMU_ALLOCCFG_LEN    4
#define SMMU_ALLOCCFG_OFFSET 8
#define SMMU_MTCFG_LEN       1
#define SMMU_MTCFG_OFFSET    4
#define SMMU_MEMATTR_LEN     4
#define SMMU_MEMATTR_OFFSET  0

#define SMMU_UPDATING_LEN    1
#define SMMU_UPDATING_OFFSET 31
#define SMMU_ABORT_LEN       1
#define SMMU_ABORT_OFFSET    20
#define SMMU_INSTCFG_LEN     2
#define SMMU_INSTCFG_OFFSET  18
#define SMMU_PRIVCFG_LEN     2
#define SMMU_PRIVCFG_OFFSET  16
#define SMMU_NSCFG_LEN       2
#define SMMU_NSCFG_OFFSET    14
#define SMMU_SHCFG_LEN       2
#define SMMU_SHCFG_OFFSET    12
#define SMMU_ALLOCCFG_LEN    4
#define SMMU_ALLOCCFG_OFFSET 8
#define SMMU_MTCFG_LEN       1
#define SMMU_MTCFG_OFFSET    4
#define SMMU_MEMATTR_LEN     4
#define SMMU_MEMATTR_OFFSET  0

#define SMMU_EVENTQ_IRQEN_S_LEN    1
#define SMMU_EVENTQ_IRQEN_S_OFFSET 2
#define SMMU_PRIQ_IRQEN_S_LEN      1
#define SMMU_PRIQ_IRQEN_S_OFFSET   1
#define SMMU_GERROR_IRQEN_S_LEN    1
#define SMMU_GERROR_IRQEN_S_OFFSET 0

#define SMMU_EVENTQ_IRQEN_S_LEN    1
#define SMMU_EVENTQ_IRQEN_S_OFFSET 2
#define SMMU_PRIQ_IRQEN_S_LEN      1
#define SMMU_PRIQ_IRQEN_S_OFFSET   1
#define SMMU_GERROR_IRQEN_S_LEN    1
#define SMMU_GERROR_IRQEN_S_OFFSET 0

#define SMMU_MSI_GERROR_ABT_ERR_LEN    1
#define SMMU_MSI_GERROR_ABT_ERR_OFFSET 7
#define SMMU_MSI_EVENTQ_ABT_ERR_LEN    1
#define SMMU_MSI_EVENTQ_ABT_ERR_OFFSET 5
#define SMMU_MSI_CMDQ_ABT_ERR_LEN      1
#define SMMU_MSI_CMDQ_ABT_ERR_OFFSET   4
#define SMMU_EVENTQ_ABT_ERR_LEN        1
#define SMMU_EVENTQ_ABT_ERR_OFFSET     2
#define SMMU_CMDQ_ERR_LEN              1
#define SMMU_CMDQ_ERR_OFFSET           0

#define SMMU_MSI_GERROR_ABT_ERR_LEN    1
#define SMMU_MSI_GERROR_ABT_ERR_OFFSET 7
#define SMMU_MSI_EVENTQ_ABT_ERR_LEN    1
#define SMMU_MSI_EVENTQ_ABT_ERR_OFFSET 5
#define SMMU_MSI_CMDQ_ABT_ERR_LEN      1
#define SMMU_MSI_CMDQ_ABT_ERR_OFFSET   4
#define SMMU_EVENTQ_ABT_ERR_LEN        1
#define SMMU_EVENTQ_ABT_ERR_OFFSET     2
#define SMMU_CMDQ_ERR_LEN              1
#define SMMU_CMDQ_ERR_OFFSET           0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_RESERVERD_LEN    16
#define SMMU_RESERVERD_OFFSET 16
#define SMMU_ADDR_LEN         16
#define SMMU_ADDR_OFFSET      0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_ADDR_LEN    26
#define SMMU_ADDR_OFFSET 6

#define SMMU_RA_LEN      1
#define SMMU_RA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_FMT_LEN         2
#define SMMU_FMT_OFFSET      16
#define SMMU_SPLIT_LEN       5
#define SMMU_SPLIT_OFFSET    6
#define SMMU_LOG2SIZE_LEN    6
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_ADDR_LEN        27
#define SMMU_ADDR_OFFSET     5
#define SMMU_LOG2SIZE_LEN    5
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_RA_LEN      1
#define SMMU_RA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_WR_WRAP_LEN    1
#define SMMU_WR_WRAP_OFFSET 19
#define SMMU_WR_LEN         19
#define SMMU_WR_OFFSET      0

#define SMMU_ERR_LEN        7
#define SMMU_ERR_OFFSET     24
#define SMMU_RD_WRAP_LEN    1
#define SMMU_RD_WRAP_OFFSET 19
#define SMMU_RD_LEN         19
#define SMMU_RD_OFFSET      0

#define SMMU_ADDR_LEN        27
#define SMMU_ADDR_OFFSET     5
#define SMMU_LOG2SIZE_LEN    5
#define SMMU_LOG2SIZE_OFFSET 0

#define SMMU_WA_LEN      1
#define SMMU_WA_OFFSET   30
#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_OVFLG_LEN      1
#define SMMU_OVFLG_OFFSET   31
#define SMMU_WR_WRAP_LEN    1
#define SMMU_WR_WRAP_OFFSET 19
#define SMMU_WR_LEN         19
#define SMMU_WR_OFFSET      0

#define SMMU_OVACKFLG_LEN    1
#define SMMU_OVACKFLG_OFFSET 31
#define SMMU_RD_WRAP_LEN     1
#define SMMU_RD_WRAP_OFFSET  19
#define SMMU_RD_LEN          19
#define SMMU_RD_OFFSET       0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_ADDR_LEN    16
#define SMMU_ADDR_OFFSET 0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_PCIE_INVLD_MODE_LEN               1
#define SMMU_PCIE_INVLD_MODE_OFFSET            31
#define SMMU_MPAM_EN_LEN                       1
#define SMMU_MPAM_EN_OFFSET                    30
#define SMMU_L2_TLB_INDEX_MODE_LEN             1
#define SMMU_L2_TLB_INDEX_MODE_OFFSET          29
#define SMMU_STREAM_WRITE_MODE_TP_LEN          1
#define SMMU_STREAM_WRITE_MODE_TP_OFFSET       28
#define SMMU_STASH_DIEID1_LEN                  2
#define SMMU_STASH_DIEID1_OFFSET               26
#define SMMU_STASH_DIEID0_LEN                  2
#define SMMU_STASH_DIEID0_OFFSET               24
#define SMMU_WRITEBACK_SPILL_EN_LEN            1
#define SMMU_WRITEBACK_SPILL_EN_OFFSET         23
#define SMMU_STREAM_WRITE_MODE_SP_LEN          1
#define SMMU_STREAM_WRITE_MODE_SP_OFFSET       22
#define SMMU_READONCE_MAKEINVALID_LEN          1
#define SMMU_READONCE_MAKEINVALID_OFFSET       21
#define SMMU_STE_BYPASS_ALLOCATE_TLB_EN_LEN    1
#define SMMU_STE_BYPASS_ALLOCATE_TLB_EN_OFFSET 20
#define SMMU_STREAM_REQ_OPT_LEN                8
#define SMMU_STREAM_REQ_OPT_OFFSET             12
#define SMMU_L2_ALLOCATE_L1_EN_LEN             1
#define SMMU_L2_ALLOCATE_L1_EN_OFFSET          11
#define SMMU_SKY_BYPASS_RD_FORCE_LEN           1
#define SMMU_SKY_BYPASS_RD_FORCE_OFFSET        10
#define SMMU_SKY_BYPASS_WR_FORCE_LEN           1
#define SMMU_SKY_BYPASS_WR_FORCE_OFFSET        9
#define SMMU_SKY_BYPASS_EN_LEN                 1
#define SMMU_SKY_BYPASS_EN_OFFSET              8
#define SMMU_L2_TLB_GS_SET_LEN                 4
#define SMMU_L2_TLB_GS_SET_OFFSET              4
#define SMMU_PAGE_CACHE_EN_LEN                 1
#define SMMU_PAGE_CACHE_EN_OFFSET              3
#define SMMU_WALK_CACHE_EN_LEN                 1
#define SMMU_WALK_CACHE_EN_OFFSET              2
#define SMMU_CMD_OTS_EN_LEN                    1
#define SMMU_CMD_OTS_EN_OFFSET                 1
#define SMMU_L2_TLB_EN_LEN                     1
#define SMMU_L2_TLB_EN_OFFSET                  0

#define SMMU_MASTER7_GS_LEN    2
#define SMMU_MASTER7_GS_OFFSET 14
#define SMMU_MASTER6_GS_LEN    2
#define SMMU_MASTER6_GS_OFFSET 12
#define SMMU_MASTER5_GS_LEN    2
#define SMMU_MASTER5_GS_OFFSET 10
#define SMMU_MASTER4_GS_LEN    2
#define SMMU_MASTER4_GS_OFFSET 8
#define SMMU_MASTER3_GS_LEN    2
#define SMMU_MASTER3_GS_OFFSET 6
#define SMMU_MASTER2_GS_LEN    2
#define SMMU_MASTER2_GS_OFFSET 4
#define SMMU_MASTER1_GS_LEN    2
#define SMMU_MASTER1_GS_OFFSET 2
#define SMMU_MASTER0_GS_LEN    2
#define SMMU_MASTER0_GS_OFFSET 0

#define SMMU_VERSION_ID_LEN    32
#define SMMU_VERSION_ID_OFFSET 0

#define SMMU_PRODUCTID_LEN      12
#define SMMU_PRODUCTID_OFFSET   20
#define SMMU_VARIANT_LEN        4
#define SMMU_VARIANT_OFFSET     16
#define SMMU_REVISION_LEN       4
#define SMMU_REVISION_OFFSET    12
#define SMMU_IMPLEMENTER_LEN    12
#define SMMU_IMPLEMENTER_OFFSET 0

#define SMMU_INV_ALL_NS_LEN    1
#define SMMU_INV_ALL_NS_OFFSET 0

#define SMMU_IRPT_TOPCIE_EN_LEN    1
#define SMMU_IRPT_TOPCIE_EN_OFFSET 0

#define SMMU_IRPT_TOPCIE_ADDR_LEN    32
#define SMMU_IRPT_TOPCIE_ADDR_OFFSET 0

#define SMMU_IRPT_TOPCIE_DATA_LEN    32
#define SMMU_IRPT_TOPCIE_DATA_OFFSET 0

#define SMMU_REG_SKY_NOT_BLOCK_INT_LEN    1
#define SMMU_REG_SKY_NOT_BLOCK_INT_OFFSET 13
#define SMMU_REG_SKY_NOT_BLOCK_LEN        1
#define SMMU_REG_SKY_NOT_BLOCK_OFFSET     12
#define SMMU_REG_L2_INV_VA_MODE_LEN       1
#define SMMU_REG_L2_INV_VA_MODE_OFFSET    11
#define SMMU_REG_INV_VA_DISABLE_LEN       1
#define SMMU_REG_INV_VA_DISABLE_OFFSET    10
#define SMMU_REG_ATS_MODE_LEN             1
#define SMMU_REG_ATS_MODE_OFFSET          9
#define SMMU_REG_PRI_MODE_LEN             1
#define SMMU_REG_PRI_MODE_OFFSET          8
#define SMMU_IOCACHE_COMP_MODE_LEN        1
#define SMMU_IOCACHE_COMP_MODE_OFFSET     7
#define SMMU_PTW_INVLD_MODE_LEN           1
#define SMMU_PTW_INVLD_MODE_OFFSET        6
#define SMMU_TOCPA_EN_LEN                 1
#define SMMU_TOCPA_EN_OFFSET              5
#define SMMU_STASH_DIE_MODE_LEN           1
#define SMMU_STASH_DIE_MODE_OFFSET        4
#define SMMU_PTW_QOS_LEN                  4
#define SMMU_PTW_QOS_OFFSET               0

#define SMMU_DFX_SKY_QUEUE_PROBE_ID_LEN    8
#define SMMU_DFX_SKY_QUEUE_PROBE_ID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_LOW_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_LOW_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_HIGH_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_HIGH_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_MSTID_LEN    3
#define SMMU_DFX_SKY_QUEUE_PROBE_MSTID_OFFSET 24
#define SMMU_DFX_SKY_QUEUE_PROBE_TXNID_LEN    8
#define SMMU_DFX_SKY_QUEUE_PROBE_TXNID_OFFSET 16
#define SMMU_DFX_SKY_QUEUE_PROBE_STAT_LEN     16
#define SMMU_DFX_SKY_QUEUE_PROBE_STAT_OFFSET  0

#define SMMU_DFX_SKY_QUEUE_PROBE_STRMID_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_STRMID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_ID_LEN    8
#define SMMU_DFX_SKY_QUEUE_PROBE_ID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_LOW_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_LOW_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_HIGH_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_ADDR_HIGH_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_PROBE_MSTID_LEN    3
#define SMMU_DFX_SKY_QUEUE_PROBE_MSTID_OFFSET 24
#define SMMU_DFX_SKY_QUEUE_PROBE_TXNID_LEN    8
#define SMMU_DFX_SKY_QUEUE_PROBE_TXNID_OFFSET 16
#define SMMU_DFX_SKY_QUEUE_PROBE_STAT_LEN     16
#define SMMU_DFX_SKY_QUEUE_PROBE_STAT_OFFSET  0

#define SMMU_DFX_SKY_QUEUE_PROBE_STRMID_LEN    32
#define SMMU_DFX_SKY_QUEUE_PROBE_STRMID_OFFSET 0

#define SMMU_CMD_NUM_TP_LEN    8
#define SMMU_CMD_NUM_TP_OFFSET 8
#define SMMU_CMD_NUM_SP_LEN    8
#define SMMU_CMD_NUM_SP_OFFSET 0

#define SMMU_DFX_CMD_QUEUE_STAT_LEN    32
#define SMMU_DFX_CMD_QUEUE_STAT_OFFSET 0

#define SMMU_DFX_STALL_IRPT_TP_LEN    1
#define SMMU_DFX_STALL_IRPT_TP_OFFSET 31
#define SMMU_DFX_STALL_IRPT_SP_LEN    1
#define SMMU_DFX_STALL_IRPT_SP_OFFSET 30
#define SMMU_FAULT_CNT_LEN            30
#define SMMU_FAULT_CNT_OFFSET         0

#define SMMU_BLOCK_AXI_RD_NORDER_LONG_LEN    1
#define SMMU_BLOCK_AXI_RD_NORDER_LONG_OFFSET 21
#define SMMU_BLOCK_AXI_WR_NORDER_LONG_LEN    1
#define SMMU_BLOCK_AXI_WR_NORDER_LONG_OFFSET 20
#define SMMU_BLOCK_AXI_RD_NORDER_LEN         1
#define SMMU_BLOCK_AXI_RD_NORDER_OFFSET      19
#define SMMU_BLOCK_AXI_WR_NORDER_LEN         1
#define SMMU_BLOCK_AXI_WR_NORDER_OFFSET      18
#define SMMU_BLOCK_AXI_RD_ORDER_LEN          1
#define SMMU_BLOCK_AXI_RD_ORDER_OFFSET       17
#define SMMU_BLOCK_AXI_WR_ORDER_LEN          1
#define SMMU_BLOCK_AXI_WR_ORDER_OFFSET       16
#define SMMU_BLOCK_AXI_MST_NUM_LEN           8
#define SMMU_BLOCK_AXI_MST_NUM_OFFSET        8
#define SMMU_DFX_SKY_QUEUE_VALUD_NUM_LEN     8
#define SMMU_DFX_SKY_QUEUE_VALUD_NUM_OFFSET  0

#define SMMU_BLOCK_AXI_RD_NORDER_LONG_LEN    1
#define SMMU_BLOCK_AXI_RD_NORDER_LONG_OFFSET 21
#define SMMU_BLOCK_AXI_WR_NORDER_LONG_LEN    1
#define SMMU_BLOCK_AXI_WR_NORDER_LONG_OFFSET 20
#define SMMU_BLOCK_AXI_RD_NORDER_LEN         1
#define SMMU_BLOCK_AXI_RD_NORDER_OFFSET      19
#define SMMU_BLOCK_AXI_WR_NORDER_LEN         1
#define SMMU_BLOCK_AXI_WR_NORDER_OFFSET      18
#define SMMU_BLOCK_AXI_RD_ORDER_LEN          1
#define SMMU_BLOCK_AXI_RD_ORDER_OFFSET       17
#define SMMU_BLOCK_AXI_WR_ORDER_LEN          1
#define SMMU_BLOCK_AXI_WR_ORDER_OFFSET       16
#define SMMU_BLOCK_AXI_MST_NUM_LEN           8
#define SMMU_BLOCK_AXI_MST_NUM_OFFSET        8
#define SMMU_DFX_SKY_QUEUE_VALUD_NUM_LEN     8
#define SMMU_DFX_SKY_QUEUE_VALUD_NUM_OFFSET  0

#define SMMU_AXI_ECC_ERR_TP_CNT_LEN     8
#define SMMU_AXI_ECC_ERR_TP_CNT_OFFSET  24
#define SMMU_AXI_ECC_ERR_SP_CNT_LEN     8
#define SMMU_AXI_ECC_ERR_SP_CNT_OFFSET  16
#define SMMU_CNTXT_CACHE_ECC_CNT_LEN    8
#define SMMU_CNTXT_CACHE_ECC_CNT_OFFSET 8
#define SMMU_L2_ECC_CNT_LEN             8
#define SMMU_L2_ECC_CNT_OFFSET          0

#define SMMU_DFX_SKY_QUEUE_STALL_STRMID_LEN    25
#define SMMU_DFX_SKY_QUEUE_STALL_STRMID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_STALL_NS_LEN       1
#define SMMU_DFX_SKY_QUEUE_STALL_NS_OFFSET    8
#define SMMU_DFX_SKY_QUEUE_STALL_TXNID_LEN    8
#define SMMU_DFX_SKY_QUEUE_STALL_TXNID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_STALL_STRMID_LEN    25
#define SMMU_DFX_SKY_QUEUE_STALL_STRMID_OFFSET 0

#define SMMU_DFX_SKY_QUEUE_STALL_NS_LEN       1
#define SMMU_DFX_SKY_QUEUE_STALL_NS_OFFSET    8
#define SMMU_DFX_SKY_QUEUE_STALL_TXNID_LEN    8
#define SMMU_DFX_SKY_QUEUE_STALL_TXNID_OFFSET 0

#define SMMU_INJECT_2BIT_EN_LEN     1
#define SMMU_INJECT_2BIT_EN_OFFSET  19
#define SMMU_INJECT_TCU_EN_LEN      1
#define SMMU_INJECT_TCU_EN_OFFSET   18
#define SMMU_INJECT_TBU_EN_LEN      1
#define SMMU_INJECT_TBU_EN_OFFSET   17
#define SMMU_INJECT_AXI_EN_LEN      1
#define SMMU_INJECT_AXI_EN_OFFSET   16
#define SMMU_INJECT_2BIT_SEL_LEN    8
#define SMMU_INJECT_2BIT_SEL_OFFSET 8
#define SMMU_INJECT_1BIT_SEL_LEN    8
#define SMMU_INJECT_1BIT_SEL_OFFSET 0

#define SMMU_DFX_PTW_STATUS_0_LEN    32
#define SMMU_DFX_PTW_STATUS_0_OFFSET 0

#define SMMU_DFX_PTW_STATUS_1_LEN    32
#define SMMU_DFX_PTW_STATUS_1_OFFSET 0

#define SMMU_DFX_PTW_STATUS_2_LEN    32
#define SMMU_DFX_PTW_STATUS_2_OFFSET 0

#define SMMU_DFX_PTW_STATUS_3_LEN    32
#define SMMU_DFX_PTW_STATUS_3_OFFSET 0

#define SMMU_DFX_PTW_STATUS_S2_0_LEN    32
#define SMMU_DFX_PTW_STATUS_S2_0_OFFSET 0

#define SMMU_DFX_PTW_STATUS_S2_1_LEN    32
#define SMMU_DFX_PTW_STATUS_S2_1_OFFSET 0

#define SMMU_DFX_PTW_STATUS_S2_2_LEN    32
#define SMMU_DFX_PTW_STATUS_S2_2_OFFSET 0

#define SMMU_DFX_PTW_STATUS_S2_3_LEN    32
#define SMMU_DFX_PTW_STATUS_S2_3_OFFSET 0

#define SMMU_EVCNT_0_0_LEN    32
#define SMMU_EVCNT_0_0_OFFSET 0

#define SMMU_EVCNT_0_1_LEN    32
#define SMMU_EVCNT_0_1_OFFSET 0

#define SMMU_EVCNT_0_2_LEN    32
#define SMMU_EVCNT_0_2_OFFSET 0

#define SMMU_EVCNT_0_3_LEN    32
#define SMMU_EVCNT_0_3_OFFSET 0

#define SMMU_EVCNT_0_4_LEN    32
#define SMMU_EVCNT_0_4_OFFSET 0

#define SMMU_EVCNT_0_5_LEN    32
#define SMMU_EVCNT_0_5_OFFSET 0

#define SMMU_EVCNT_0_6_LEN    32
#define SMMU_EVCNT_0_6_OFFSET 0

#define SMMU_EVCNT_0_7_LEN    32
#define SMMU_EVCNT_0_7_OFFSET 0

#define SMMU_EVCNT_1_0_LEN    32
#define SMMU_EVCNT_1_0_OFFSET 0

#define SMMU_EVCNT_1_1_LEN    32
#define SMMU_EVCNT_1_1_OFFSET 0

#define SMMU_EVCNT_1_2_LEN    32
#define SMMU_EVCNT_1_2_OFFSET 0

#define SMMU_EVCNT_1_3_LEN    32
#define SMMU_EVCNT_1_3_OFFSET 0

#define SMMU_EVCNT_1_4_LEN    32
#define SMMU_EVCNT_1_4_OFFSET 0

#define SMMU_EVCNT_1_5_LEN    32
#define SMMU_EVCNT_1_5_OFFSET 0

#define SMMU_EVCNT_1_6_LEN    32
#define SMMU_EVCNT_1_6_OFFSET 0

#define SMMU_EVCNT_1_7_LEN    32
#define SMMU_EVCNT_1_7_OFFSET 0

#define SMMU_OVFCAP_0_LEN             1
#define SMMU_OVFCAP_0_OFFSET          31
#define SMMU_FILTER_SEC_SID_0_LEN     1
#define SMMU_FILTER_SEC_SID_0_OFFSET  30
#define SMMU_FILTER_SID_SPAN_0_LEN    1
#define SMMU_FILTER_SID_SPAN_0_OFFSET 29
#define SMMU_EVENT_0_LEN              16
#define SMMU_EVENT_0_OFFSET           0

#define SMMU_OVFCAP_1_LEN             1
#define SMMU_OVFCAP_1_OFFSET          31
#define SMMU_FILTER_SEC_SID_1_LEN     1
#define SMMU_FILTER_SEC_SID_1_OFFSET  30
#define SMMU_FILTER_SID_SPAN_1_LEN    1
#define SMMU_FILTER_SID_SPAN_1_OFFSET 29
#define SMMU_EVENT_1_LEN              16
#define SMMU_EVENT_1_OFFSET           0

#define SMMU_OVFCAP_2_LEN             1
#define SMMU_OVFCAP_2_OFFSET          31
#define SMMU_FILTER_SEC_SID_2_LEN     1
#define SMMU_FILTER_SEC_SID_2_OFFSET  30
#define SMMU_FILTER_SID_SPAN_2_LEN    1
#define SMMU_FILTER_SID_SPAN_2_OFFSET 29
#define SMMU_EVENT_2_LEN              16
#define SMMU_EVENT_2_OFFSET           0

#define SMMU_OVFCAP_3_LEN             1
#define SMMU_OVFCAP_3_OFFSET          31
#define SMMU_FILTER_SEC_SID_3_LEN     1
#define SMMU_FILTER_SEC_SID_3_OFFSET  30
#define SMMU_FILTER_SID_SPAN_3_LEN    1
#define SMMU_FILTER_SID_SPAN_3_OFFSET 29
#define SMMU_EVENT_3_LEN              16
#define SMMU_EVENT_3_OFFSET           0

#define SMMU_OVFCAP_4_LEN             1
#define SMMU_OVFCAP_4_OFFSET          31
#define SMMU_FILTER_SEC_SID_4_LEN     1
#define SMMU_FILTER_SEC_SID_4_OFFSET  30
#define SMMU_FILTER_SID_SPAN_4_LEN    1
#define SMMU_FILTER_SID_SPAN_4_OFFSET 29
#define SMMU_EVENT_4_LEN              16
#define SMMU_EVENT_4_OFFSET           0

#define SMMU_OVFCAP_5_LEN             1
#define SMMU_OVFCAP_5_OFFSET          31
#define SMMU_FILTER_SEC_SID_5_LEN     1
#define SMMU_FILTER_SEC_SID_5_OFFSET  30
#define SMMU_FILTER_SID_SPAN_5_LEN    1
#define SMMU_FILTER_SID_SPAN_5_OFFSET 29
#define SMMU_EVENT_5_LEN              16
#define SMMU_EVENT_5_OFFSET           0

#define SMMU_OVFCAP_6_LEN             1
#define SMMU_OVFCAP_6_OFFSET          31
#define SMMU_FILTER_SEC_SID_6_LEN     1
#define SMMU_FILTER_SEC_SID_6_OFFSET  30
#define SMMU_FILTER_SID_SPAN_6_LEN    1
#define SMMU_FILTER_SID_SPAN_6_OFFSET 29
#define SMMU_EVENT_6_LEN              16
#define SMMU_EVENT_6_OFFSET           0

#define SMMU_OVFCAP_7_LEN             1
#define SMMU_OVFCAP_7_OFFSET          31
#define SMMU_FILTER_SEC_SID_7_LEN     1
#define SMMU_FILTER_SEC_SID_7_OFFSET  30
#define SMMU_FILTER_SID_SPAN_7_LEN    1
#define SMMU_FILTER_SID_SPAN_7_OFFSET 29
#define SMMU_EVENT_7_LEN              16
#define SMMU_EVENT_7_OFFSET           0

#define SMMU_SVR0_0_LEN    32
#define SMMU_SVR0_0_OFFSET 0

#define SMMU_SVR0_1_LEN    32
#define SMMU_SVR0_1_OFFSET 0

#define SMMU_SVR0_2_LEN    32
#define SMMU_SVR0_2_OFFSET 0

#define SMMU_SVR0_3_LEN    32
#define SMMU_SVR0_3_OFFSET 0

#define SMMU_SVR0_4_LEN    32
#define SMMU_SVR0_4_OFFSET 0

#define SMMU_SVR0_5_LEN    32
#define SMMU_SVR0_5_OFFSET 0

#define SMMU_SVR0_6_LEN    32
#define SMMU_SVR0_6_OFFSET 0

#define SMMU_SVR0_7_LEN    32
#define SMMU_SVR0_7_OFFSET 0

#define SMMU_SVR1_0_LEN    32
#define SMMU_SVR1_0_OFFSET 0

#define SMMU_SVR1_1_LEN    32
#define SMMU_SVR1_1_OFFSET 0

#define SMMU_SVR1_2_LEN    32
#define SMMU_SVR1_2_OFFSET 0

#define SMMU_SVR1_3_LEN    32
#define SMMU_SVR1_3_OFFSET 0

#define SMMU_SVR1_4_LEN    32
#define SMMU_SVR1_4_OFFSET 0

#define SMMU_SVR1_5_LEN    32
#define SMMU_SVR1_5_OFFSET 0

#define SMMU_SVR1_6_LEN    32
#define SMMU_SVR1_6_OFFSET 0

#define SMMU_SVR1_7_LEN    32
#define SMMU_SVR1_7_OFFSET 0

#define SMMU_SMR_0_LEN    32
#define SMMU_SMR_0_OFFSET 0

#define SMMU_SMR_1_LEN    32
#define SMMU_SMR_1_OFFSET 0

#define SMMU_SMR_2_LEN    32
#define SMMU_SMR_2_OFFSET 0

#define SMMU_SMR_3_LEN    32
#define SMMU_SMR_3_OFFSET 0

#define SMMU_SMR_4_LEN    32
#define SMMU_SMR_4_OFFSET 0

#define SMMU_SMR_5_LEN    32
#define SMMU_SMR_5_OFFSET 0

#define SMMU_SMR_6_LEN    32
#define SMMU_SMR_6_OFFSET 0

#define SMMU_SMR_7_LEN    32
#define SMMU_SMR_7_OFFSET 0

#define SMMU_CNTEN_LEN    32
#define SMMU_CNTEN_OFFSET 0

#define SMMU_CNTEN_LEN    32
#define SMMU_CNTEN_OFFSET 0

#define SMMU_CNTCLR_LEN    32
#define SMMU_CNTCLR_OFFSET 0

#define SMMU_CNTCLR_LEN    32
#define SMMU_CNTCLR_OFFSET 0

#define SMMU_INTEN_LEN    32
#define SMMU_INTEN_OFFSET 0

#define SMMU_INTEN_LEN    32
#define SMMU_INTEN_OFFSET 0

#define SMMU_INTCLR_LEN    32
#define SMMU_INTCLR_OFFSET 0

#define SMMU_INTCLR_LEN    32
#define SMMU_INTCLR_OFFSET 0

#define SMMU_OVS_LEN    32
#define SMMU_OVS_OFFSET 0

#define SMMU_OVS_LEN    32
#define SMMU_OVS_OFFSET 0

#define SMMU_OVS_LEN    32
#define SMMU_OVS_OFFSET 0

#define SMMU_OVS_LEN    32
#define SMMU_OVS_OFFSET 0

#define SMMU_CAPTURE_LEN    1
#define SMMU_CAPTURE_OFFSET 0

#define SMMU_READONE_LEN    1
#define SMMU_READONE_OFFSET 31
#define SMMU_NSMSI_LEN      1
#define SMMU_NSMSI_OFFSET   2
#define SMMU_NSRA_LEN       1
#define SMMU_NSRA_OFFSET    1
#define SMMU_SO_LEN         1
#define SMMU_SO_OFFSET      0

#define SMMU_SID_FILTER_TYPE_LEN    1
#define SMMU_SID_FILTER_TYPE_OFFSET 23
#define SMMU_CAPTURE_LEN            1
#define SMMU_CAPTURE_OFFSET         22
#define SMMU_MSI_LEN                1
#define SMMU_MSI_OFFSET             21
#define SMMU_RELOC_CTRS_LEN         1
#define SMMU_RELOC_CTRS_OFFSET      20
#define SMMU_SIZE_LEN               6
#define SMMU_SIZE_OFFSET            8
#define SMMU_NCTR_LEN               6
#define SMMU_NCTR_OFFSET            0

#define SMMU_E_LEN    1
#define SMMU_E_OFFSET 0

#define SMMU_EVENT_EN_LEN    32
#define SMMU_EVENT_EN_OFFSET 0

#define SMMU_EVENT_EN_LEN    32
#define SMMU_EVENT_EN_OFFSET 0

#define SMMU_EVENT_EN_LEN    32
#define SMMU_EVENT_EN_OFFSET 0

#define SMMU_EVENT_EN_LEN    32
#define SMMU_EVENT_EN_OFFSET 0

#define SMMU_IRQEN_LEN    1
#define SMMU_IRQEN_OFFSET 0

#define SMMU_IRQEN_LEN    1
#define SMMU_IRQEN_OFFSET 0

#define SMMU_ADDR_LEN    30
#define SMMU_ADDR_OFFSET 2

#define SMMU_ADDR_LEN    20
#define SMMU_ADDR_OFFSET 0

#define SMMU_DATA_LEN    32
#define SMMU_DATA_OFFSET 0

#define SMMU_SH_LEN         2
#define SMMU_SH_OFFSET      4
#define SMMU_MEMATTR_LEN    4
#define SMMU_MEMATTR_OFFSET 0

#define SMMU_IRQ_ABT_LEN    1
#define SMMU_IRQ_ABT_OFFSET 0

#define SMMU_ARCHMAJORREV_LEN    4
#define SMMU_ARCHMAJORREV_OFFSET 4
#define SMMU_ARCHMINORREV_LEN    4
#define SMMU_ARCHMINORREV_OFFSET 0

#define SMMU_CEO_LEN    2
#define SMMU_CEO_OFFSET 18
#define SMMU_DUI_LEN    2
#define SMMU_DUI_OFFSET 16
#define SMMU_RP_LEN     1
#define SMMU_RP_OFFSET  15
#define SMMU_CEC_LEN    3
#define SMMU_CEC_OFFSET 12
#define SMMU_CFI_LEN    2
#define SMMU_CFI_OFFSET 10
#define SMMU_UE_LEN     2
#define SMMU_UE_OFFSET  8
#define SMMU_FI_LEN     2
#define SMMU_FI_OFFSET  6
#define SMMU_UI_LEN     2
#define SMMU_UI_OFFSET  4
#define SMMU_ED_LEN     2
#define SMMU_ED_OFFSET  0



#define SMMU_DUI_LEN    1
#define SMMU_DUI_OFFSET 10
#define SMMU_CFI_LEN    1
#define SMMU_CFI_OFFSET 8
#define SMMU_UE_LEN     1
#define SMMU_UE_OFFSET  4
#define SMMU_FI_LEN     1
#define SMMU_FI_OFFSET  3
#define SMMU_UI_LEN     1
#define SMMU_UI_OFFSET  2
#define SMMU_ED_LEN     1
#define SMMU_ED_OFFSET  0



#define SMMU_AV_LEN      1
#define SMMU_AV_OFFSET   31
#define SMMU_V_LEN       1
#define SMMU_V_OFFSET    30
#define SMMU_UE_LEN      1
#define SMMU_UE_OFFSET   29
#define SMMU_ER_LEN      1
#define SMMU_ER_OFFSET   28
#define SMMU_OF_LEN      1
#define SMMU_OF_OFFSET   27
#define SMMU_MV_LEN      1
#define SMMU_MV_OFFSET   26
#define SMMU_CE_LEN      2
#define SMMU_CE_OFFSET   24
#define SMMU_DE_LEN      1
#define SMMU_DE_OFFSET   23
#define SMMU_PN_LEN      1
#define SMMU_PN_OFFSET   22
#define SMMU_UET_LEN     2
#define SMMU_UET_OFFSET  20
#define SMMU_IERR_LEN    8
#define SMMU_IERR_OFFSET 8
#define SMMU_SERR_LEN    8
#define SMMU_SERR_OFFSET 0



#define SMMU_ERR_ADDR_LOW_LEN    32
#define SMMU_ERR_ADDR_LOW_OFFSET 0

#define SMMU_ADDR_NS_LEN          1
#define SMMU_ADDR_NS_OFFSET       31
#define SMMU_ADDR_AI_LEN          1
#define SMMU_ADDR_AI_OFFSET       29
#define SMMU_RSERVED_LEN          13
#define SMMU_RSERVED_OFFSET       16
#define SMMU_ERR_ADDR_HIGH_LEN    16
#define SMMU_ERR_ADDR_HIGH_OFFSET 0



#define SMMU_ECC_ERR_OVFLOW_LEN    1
#define SMMU_ECC_ERR_OVFLOW_OFFSET 7
#define SMMU_ECC_ERR_CNT_LEN       7
#define SMMU_ECC_ERR_CNT_OFFSET    0





#endif // __SMMU_REG_OFFSET_FIELD_H__
